Field
The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of defining routing tracks for a standard cell semiconductor device, and to the standard cell semiconductor device.
Description of the Related Technology
In semiconductor fabrication, standard cell methodology typically involves designing integrated circuits having various functionality using standard components and interconnected structures. Standard cell methodology uses an abstraction wherein low level integrated synthesis is replaced by a more high-level aspect of design. A standard cell can be made up of a group of transistor structures, passive structures, and interconnect structures that make up, e.g., logic functions, storage functions or the like.
As integrated circuits continue to scale while incorporating an increasing number of electronic components and functionalities within a given area, there is a strive for reducing the size of standard cells.
Multiple patterning is a technology that has been developed to enhance the feature density of the integrated circuits as the separation between neighboring features, such as, e.g., the routing tracks, approaches the wavelength of light used in a photolithographic method. In this technology, the complete pattern may be divided into two or more sub-patterns which are defined by individual sub-masks. The complete pattern may then be produced by transferring one sub-pattern at a time, using the corresponding sub-mask.
Even though such a technology may allow for a reduced standard cell area, there is still a need for improved methods and devices allowing for a further reduction of the cell size.